-
-
Notifications
You must be signed in to change notification settings - Fork 4
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
OvmfPkg: DxeTcg2PhysicalPresenceLib: fix changing of PCR banks #164
Conversation
Tcg2PhysicalPresenceLibSubmitRequestToPreOSFunction writes to TPM2 physical presence PPI provided by coreboot (a memory region preserved across reboots). CPU caches must be explicitly flushed prior to platform reboot or request written to PPI will be lost. Signed-off-by: Artur Kowalski <[email protected]>
8294b19
to
1f42592
Compare
@arturkow2 please do not open PRs based outdated history of target branch... Be sure to pull most recent code before yo ubranch out for development. I already rebased this branch on dasharo. |
I have tested the changes on VP6650 with Infineon dTPM and it didn't work... I was not prompted to confirm the SHA bank change before entering boot menu or setup. EDIT: Wait, this platform is actually the worst possible piece to test this on. This platform can't reset properly, as it always goes through power cycle... |
Ok it works, but once I apply new PCR banks settings and reset the platform I am stuck on the prompt to change PCR banks forever:
I have to press ESC to exit the loop. It looks like the request is not cleared after it is serviced. We have to clear it so that it does not persist in RAM and is handled on each boot... This behavior was observed on VP4670 |
Flush cache not only when placing request in PPI, but also after clearing old request from PPI. Signed-off-by: Artur Kowalski <[email protected]>
fd05f33
to
2dfe3b2
Compare
Signed-off-by: Michał Żygowski <[email protected]>
Ok, now it works when the request is cleared and flushed |
Tcg2PhysicalPresenceLibSubmitRequestToPreOSFunction writes to TPM2 physical presence PPI provided by coreboot (a memory region preserved across reboots). CPU caches must be explicitly flushed prior to platform reboot or request written to PPI will be lost.